1. Field of the Invention
The invention relates to low noise frequency synthesis. More particularly, the invention concerns using a multiplier and a phase locked loop to synthesize a high frequency signal that has a desired frequency and low noise.
2. Description of the Related Art
In a variety of applications, there is a need to produce signals having specific frequencies. For example, specific carrier frequencies are often required for both analog and digital telecommunications.
A category of fiber-optic communication standards known as "SONET" (acronym for Synchronous Optical Network) provide for high speed digital communications at data rates ranging from about 51 megabits per second (or MHz) to about 39 gigabits per second (or GHz). Each of the SONET standards requires data to be clocked at a respective specific frequency. For example, the OC-48 SONET standard, which is typically used for wide area network (WAN) telecommunications, specifies a data rate of 2.48832 gigabits per second. Consequently, OC-48 telecommunications systems must have the ability to generate signals at the 2.48832 GHz rate to clock data to a laser that is connected to the fiber.
Phase locked loops (PLLs) have been widely used to synthesize signals having specific desired frequencies. In many applications the output of a PLL is referred to as a carrier, or as a synthesized clock frequency. A typical PLL 100 is illustrated in FIG. 1. The PLL includes a phase detector 105, a low pass filter 110, a voltage controlled oscillator (VCO) 115, and a divider 120. A reference signal having a known reference frequency (commonly produced by a crystal oscillator), is connected to a first input 125 of the phase detector. The output signal from the output 127 phase detector is connected to the input 130 of the low pass filter, and the output 132 of the low pass filter is connected to the input 135 of the VCO. The output 140 of the VCO, which is also the output of the PLL, is connected to the input of the divider 145, and the output of the divider 147 is connected to a second input 150 of the phase detector. The phase detector produces an output voltage that is representative of the phase difference between the reference signal and the output of the divider. The phase detector output voltage is filtered by the low pass filter, and is then used to control the output frequency of the VCO. If the frequency of the two input signals to the phase detector is the same, then the output voltage of the phase detector will remain unchanged, causing the output frequency of the VCO to remain unchanged. If the phase detector detects a phase (frequency) difference between the phase detector input signals, then the output voltage of the phase detector will change accordingly, thereby causing the frequency of the output of the VCO to increase or decrease to eliminate the phase difference between the input signals to the phase detector. In this way the frequency of the signal at the output of the divider is "locked" equal to the reference frequency. The output frequency of the VCO, which is the output of the PLL, can be locked to a frequency that is a multiple of the reference frequency by causing the divider to divide the VCO output signal by an integer value greater than one before the VCO output signal is input into the second input of the phase detector. The number that the VCO output signal is divided by is referred to as the PLL divider ratio "n".
Undesirably, PLLs produce noise in the PLL output signal which can degrade system performance. Typically, the most significant noise component in the output signals of PLLs is jitter, which can be described as variations in the time at which signal transitions take place. A common cause of jitter is duty cycle distortion. The frequency bandwidth, with reference to the carrier frequency, in which jitter can degrade performance is referred to as the jitter passband. For SONET, the jitter passband is from about 12 KHz (or generally, for practical purposes from 0 Hz) to about 20 MHz from the carrier frequency, and the major jitter components are inside the PLL closed loop bandwidth, which is approximately 1 MHz. The noise inside a PLL loop closed loop bandwidth is N0+20 log(n), with "N0" being the noise in the frequency reference signal, and "n" being the divider ratio of the PLL. Consequently, the closed loop noise inside a PLL loop bandwidth can be no better than 20 log(n). In order to reduce noise, it is desirable to minimize n. However, values of n that are larger than desirable are oftentimes required due to practical upper limits on the frequency of the reference signal that may exist, for example, as a result of crystal brittleness, vibration, or excessive cost. For example, the practical maximum reference signal frequency for SONET OC-48 systems is about 155.5 MHz, which requires a divider ratio n=16 in order to generate the required 2.488 GHz clock signal. In this instance the amount of noise above the noise reference floor is 20 log(16)=24 dB. System performance could be improved if the amount of noise could be reduced. Consequently, there is a need for a way to synthesize frequencies, but with reduced noise.